The present invention relates generally to test structures utilized in semiconductor manufacturing, and, more particularly, to test structures formed in scribe lines which offer multiple testing configurations.
As interconnect dimensions scale to smaller sizes, oxide layers become less robust, and current densities increase in today""s integrated circuits, the reliability of interconnects becomes a greater concern due to, for example, metal diffusion, barrier breakdown, oxide failure, and increased electromigration effects. Electromigration (EM), which is the diffusion of atoms in an interconnect induced by an electric current, can lead to interconnect failure by voiding or extrusion at sites along the interconnect. Furthermore, electromigration is generally temperature dependent, wherein thermal gradients due to joule heating can increase the EM effects. Tensile and compressive stresses can develop in a variety ways within the interconnect, for example, due to a difference in temperature at which dielectric layers and metallization layers are processed in the formation of the circuit. Failure of the interconnect may occur, for example, once stress somewhere in the interconnect exceeds a critical stress. Therefore, test structures are conventionally incorporated into a circuit layout on a wafer. However, the test structures must be properly designed and constructed so as to detect these potential failures when tested. The test structures may also provide utility for process development and tuning, as well as for performance comparison purposes. Typically, the test structure may be formed, for example, using metal conductive layers such as aluminum or copper.
FIG. 1A illustrates a cross-sectional view of an interconnect test structure 100 having a first conductor 105 (e.g., a cathode), a second conductor 110, and a third conductor 115 (e.g., an anode). The second conductor 110 generally forms an interconnect line between the first conductor 105 and the third conductor 115. FIG. 1A further illustrates a common failure mode, wherein voids 120 are formed near the region of the first conductor 105 due to a flow of electrical current and temperature gradients associated therewith. Voids 120 are typically paired with hillocks 125, that is, areas of metal accumulation, downstream in the electron flow. Hillocks 125 may cause, for example, metal filaments to extend from the second conductor 110 thereby forming paths of high current leakage. If the hillocks 125 are of a sufficient magnitude, a force exerted by the hillocks in the second conductor 110 (e.g., hillocks in a metal interconnect) may crack a surrounding barrier or dielectric material. Therefore, electrical and/or thermal stress testing of various types of interconnect structures is useful for determining the current density limits that circuit design engineers use in the design of product interconnect to assure maximum performance without sacrificing reliability.
Electromigration of atoms or ions from one point to another within the metal structure may cause a void at a location originally occupied by the moving atom, or alternatively, a deposition or growth at another location of the metal. In many configurations of integrated circuits, void formation very often decreases the life of the circuit, or may even result in failure of the circuit, thereby resulting in failure of a chip or system containing the circuit. The geometry of metallic interconnect lines associated with integrated circuits are generally thin and narrow, for example, less than a few tenths of a micron in depth and less than one-tenth of a micron in width, wherein electromigration may induce a void that results in a significant decrease in cross-sectional area of the electrically conductive material across the depth of width of the conductive line. Decreasing the volume of metal in the conductive path will tend to cause an increase in electrical resistance or failure of the line, or may even result in an open-circuit line. Therefore, it is highly desirable to be able to characterize electromigration properties as well as other properties of an interconnect system so as to determine a cumulative failure distribution, a median life time to failure (MTTF), the activation energy of interfacial diffusion, grain boundary or bulk diffusion, and the current density dependence.
In the past, such characterization data has been obtained through conventional DC electromigration tests performed on a packaged test chip or by wafer-level testing. To accelerate the wear of components, the test structures should endure stress current densities above the maximum used in product designs, (e.g., one million amps per square centimeter and higher), and elevated temperatures (e.g., on the order of about 150xc2x0 C. to 250xc2x0 C.) Furthermore, conventional test chips, or xe2x80x9cplug barsxe2x80x9d, placed onto product wafers consumed significant amounts of wafer area which could otherwise be utilized for production chips. Problems associated with test chips (also called process monitor chips or xe2x80x9cPMCsxe2x80x9d) may furthermore involve discrepancies in field densities across a wafer. For example, an SRAM chip comprises very densely populated structures and metal layers. A PMC formed on the same wafer, on the other hand, is generally sparsely populated as compared to the SRAM chip, and processes such as chemical mechanical polishing of metal layers may have a tendency to cause dishing in metal lines.
Another problem associated with test chips is that the test is conventionally conducted after the complete assembly of the chip. In a typical manufacture of a semiconductor chip, a large number of chips are generally formed on a single semiconductive wafer. Furthermore, numerous steps are typically performed subsequent to the formation of the chips on the wafer during final assembly, such that a long period of time may elapse before the final product is completed and ready for this testing. This typically means that all of the subsequent manufacturing steps and assembly must be completed, and assembly must be at least partially complete before the conventional type of lifetime testing or characterization of the test chip can be performed to determine whether or not the metal interconnect layers are satisfactory.
In order to avoid some of the problems associated with PMCs and to optimize wafer area utilization, test structures have been moved from the usable chip areas to scribe lines. Scribe lines are the areas of a wafer which generally separate individual chips, wherein a diamond saw utilized in separating the chips generally cuts once the chip is finalized. FIG. 1B illustrates one prior art test structure 175 utilized for electromigration testing purposes, wherein the test structure resides within a scribe line 180. The test structure 175 comprises a plurality of solid pads 182, wherein a test probe (not shown) is operable to electrically contact the plurality of solid pads to induce an electrical current from a current source 184 and measure a voltage via a voltmeter 186 across the a conductive line 188 such as a bow-tie lead. The test structure 175 of the prior art, however, may suffer from several deficiencies. For example, in order to adequately accommodate the test probe, the solid pads 182 generally consume much of the width W of the scribe line, leaving only a small portion 190 available for the conductive line 188. The portion 190 of the scribe line 180 is usually limited to accommodating a limited number of conductive lines 188 in order to avoid encroachment onto the production chip area. Furthermore, there is typically not enough available area in the scribe line for the test structures of the prior art to characterize more than a few metal layers. Since other modules also occupy typical scribe lines, such as alignment marks for lithography and modules for characterizing transistor and diode quality, there is typically not enough space for adequate scribe line structures for characterizing back-end structures.
Accordingly, it is an object of the present invention to provide a test structure formed within the scribe line which incorporates various novel test structures and interconnect structures at various metal layers, such that the above mentioned problems are avoided or eliminated. Furthermore, an appropriate test structure is needed, wherein the test structure comprises multiple devices in order to detect various failure mechanisms and processing problems.
The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Its purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.
The present invention relates generally to a test structure formed over a semiconductor substrate. According to one exemplary aspect of the present invention, a test structure is formed within a scribe line of a semiconductor substrate. The scribe line is characterized by a length and width associated with a surface of the wafer, as well as a height associated with a distance from active devices or conductive and insulating features implanted into the substrate on the surface of the wafer. The test structure comprises a plurality of patterned oxide layers with etched trenches filled with electrically conductive metal layers, wherein the plurality of metal layers are formed over the substrate and spaced along the height of the scribe line, and wherein one or more insulating layers are disposed between the plurality of metal layers.
According to one aspect of the invention, the plurality of metal layers formed within the scribe line further comprises one or more lower metal layers, wherein the one or more lower metal layers each comprises one or more split pads. The one or more split pads are longitudinally spaced along the length of the scribe line. The split pads comprise two pad portions oppositely disposed from one another and separated by a predetermined distance, whereby a channel is defined between the split pads. The channel furthermore traverses the length of the scribe line.
The plurality of metal layers further comprise a top metal layer formed over the one or more lower metal layers, wherein the top metal layer comprises a plurality of solid pads longitudinally spaced along the length of the scribe line. According to one exemplary aspect of the invention, two or more of the plurality of solid pads generally reside over two or more respective split pads associated with at least one lower metal layer, whereby two or more respective columns of pads are defined. The two or more columns of pads are furthermore spaced along the length of the scribe line in accordance with the spacing of the plurality of solid pads.
One or more longitudinal conduits associated with one or more lower metal layers are furthermore disclosed, wherein the one or more conduits electrically connect two or more of the split pads associated with the respective one or more lower metal layers. The one or more conduits generally reside within the channel between the split pads and at least one of the conduits is characterized by a first width and a second width, wherein the first width is larger than the second width, thereby defining a bow-tie lead. The test structure further comprises a plurality of pad vias, wherein the plurality of pad vias electrically connect the respective split pads and solid pads associated with the respective two or more columns of pads.
According to yet another exemplary aspect of the invention, the test structure further comprises two or more conduits associated with two or more of the lower metal layers. Furthermore, the test structure comprises one or more electrically conductive lead vias extending between the two or more conduits, thereby electrically connecting the two or more conduits therein. According to still another exemplary aspect of the invention, a multitude of combinations of longitudinal conduits and lead vias are combined to define a cascading test structure, wherein multiple metal layers comprising multiple test structures are formed.